(1) Field of the Invention
This invention relates to the methods used to fabricate semiconductor devices, and more specifically to a method of planarizing semiconductor structures using spin on glass and etch back processes.
(2) Description of Prior Art
The trend in the semiconductor industry has been to continually increase device performance, while still maintaining or decreasing the cost of semiconductor devices. These objectives have been partially satisfied by micro-miniaturazation, or the ability to produce semiconductor devices with sub-micron features. Advances in the photolithographic discipline, in terms of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials have allowed sub-micron images in photoresist to be routinely achieved. In addition similar advances in the dry etching discipline has allowed the sub-micron images in photoresist to be successfully defined, in underlying materials that are used in the fabrication of semiconductor chips.
The use of sub-micron features however, can create new problem areas that have to be addressed by the semiconductor engineering community. For example the use of sub-micron metal interconnects, with sub-micron spaces between metal interconnects, has created a problem in terms of using standard dielectric passivation processes to successfully insulate specific metal interconnects. To satisfy the conductivity, as well as the reliability requirements, in terms of current density for electromigration resistance, the narrower metal interconnects have to be thicker. This together with the narrower spaces now used between metal lines, result in aspect ratios that conventional insulator deposition processes have difficulty in successfully filling. Several processes, such as the use of spin on glass, (SOG), and chemical mechanical polishing, (CMP), have been used in an attempt to solve the problem of filling narrow spaces between metal interconnect lines. For example Allman, et al, in U.S. Pat. No. 5,312,512, describe the use of both SOG deposition, and CMP planarazation processes, in the fabrication of integrated circuits using multi-level metallizations.
Another problem encountered with narrow metal lines is the ability to successfully fabricate the connection between overlying and underlying metallization levels. Via holes, created in the dielectric layer used between metallization levels, filled with a metal, are normally used for this purpose. However to reliably create the metal filled via, a large surface area of the underlying metallization level is needed to guarantee that the via totally resides on the underlying metallization level. This increased layout demand negatively impacts semiconductor device packing density, ultimately resulting in less semiconductor chips being fabricated from a specific diameter, starting substrate. The use of a pillar technology increases, or extends the available surface area of the underlying metallization level, enabling successful via hole formation to occur. Fisher, et al, in U.S. Pat. No. 4,917,759, describe the use of a pillar technology, for use in the formation of vias, to be used to connect metallization levels. However these inventions, Fisher, et al, as well as Allman, et al, do not teach the processes needed to fabricate advanced semiconductor devices. This invention will feature a metal pillar, with an overlying metallization layer, used to extend the available surface area of this metallization level in terms of accepting a via hole. This invention also features the use of SOG insulation, for purposes of filling narrow spaces between metal features, and dry etching processing for etching back the SOG layer. However in this invention the porous SOG layer is passivated during subsequent via hole openings, as well as during subsequent metal depositions, thus not allowing deleterious outgassing to occur, which can adversely influence the properties of the depositing metal.